Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
Design-Reuse

Functional Verification Basics: UVM Tutorial

UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, ...
EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
Design-Reuse

Guidelines for Successful SoC Verification in OVM/UVM

With the increasing adoption of OVM/UVM, there is a growing demand for guidelines and best practices to ensure successful SoC verification. It is true that the verification problems did not change but ...
Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Semiconductor Engineering

Inside UVM

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...